Frequently in integrated circuits, there is a need to model the delay of a signal through a particular path so that, for example, the delay can be matched. As just one example, in a delay-locked loop (DLL), a feedback delay model circuit models the delay of a clock signal through an input and/or an output stage of the DLL. This modeled delay is then used to calibrate the DLL in order to for it to lock an output clock signal with an external clock signal by compensating for the modeled delay. Generally, the more accurate the delay model, the more accurate the DLL and the DLL lock will be, and so it can be advantageous to have a relatively accurate delay model.
Accurate delay models, however, typically consume large amounts of power, which can be disadvantageous due to the cost of and heat generated by such power consumption. One example of a relatively accurate delay model is a circuit that replicates the signal path almost exactly—i.e., the delay model is nearly identical to, though at least partially separate and distinct from, the actual path being modeled. Such an accurate delay model may include a portion of the actual path itself (e.g., when modeling a DLL output delay in the DLL feedback delay model, the accurate delay model may include a portion of the clock distribution circuit) in some but not all such accurate models.
In order to decrease the power consumed by a delay model relative to these accurate delay model circuits, the signal path can instead be modeled with a low power delay model, which may include for example smaller gates and smaller wires (e.g., minimum size gates and wires) than an accurate delay model. The low power model may also include one or more resistors and/or capacitors. These relatively low power delay models can effectively model the delay of a signal through a path while consuming relatively little power as compared with an accurate delay model. However, these low power delay models are typically not as accurate as a model that uses, for example, full size gates and wires that identically match the actual signal path. These low power delay models may not be as accurate due to the fact that, for example, process, temperature, and voltage variations affect a smaller size inverter differently than a much larger inverter. As another example, if different types of materials are used in the low power model than in the path being modeled (e.g., polysilicon is used in the low power model to model a metal wire in the path), process, temperature, and voltage variations can affect the operation of the different materials in different manners.
During design and manufacture, low power delay models can be adjusted in order to model a signal path as best as possible (e.g., can be tuned for a particular voltage and temperature corner). However, this type of adjustment is generally static and cannot be changed once the circuit is manufactured. Hence, if the temperature or voltage of the circuit changes during operation and does not match the parameters used to statically adjust the low power delay model, these dynamic changes will cause the low power delay model to be less accurate due to the disparate effect the temperature and voltage variations have on the low power model as compared with the path being modeled. Similarly, if the process used to manufacture the low power and/or the modeled path is slightly different than expected, the low power delay model may not correctly model the signal path.